The present invention relates to the field of electronic circuits, and in particular, a phase frequency detector circuit.
Many electronic systems use a master clock signal to synchronize the operation of all the circuitry and integrated circuit. A fundamental concept in electronic design, synchronous operation is important to ensure that logic operations are being performed correctly. In a system, an integrated circuit may generate its own internal clock based on the master clock signal. For example, this integrated circuit may be a microprocessor, ASIC, PLD, FPGA, or memory. The internal clock is synchronized with the master clock. And in order to ensure proper operation, it is often important to reduce skew for the internal clock of the integrated circuit.
The integrated circuit may use an on-chip clock synchronization circuit such as a phase locked loop (PLL) or delay locked loop (DLL). The synchronization circuit locks or maintains a specific phase relationship between the master clock and the internal clock. When the system is started, it is desirable that the internal clock be locked to the master clock as rapidly as possible. Under some circumstances, such as when there is a wide frequency difference between the two clock, the locking time may be slow. This is because the locking time may be dependent on the slower of the two frequencies. A slower locking time is undesirable because it will take longer for the system to initialize before normal operation. Also, as the master clock varies, it will take longer for the clock synchronization circuit to track these variations.
Therefore, techniques and circuitry are needed to address this problem of clock synchronization circuitry with slow lock acquisition times.
The invention is a phase frequency detector circuit to compare two clock signals and generate a number of outputs to indicate the phase difference between the two clock signals. This circuitry may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. In a PLL or DLL implementation, one of the clocks would be the reference clock or REFCLK, which the user supplies. The other clock is an internally generated clock or CLK that is fed back to the phase frequency detector circuit. In an embodiment, the phase frequency detector circuit has greater than three states. By having a greater numbers of states, the phase frequency detector will be able to generate a more rapidly. The DLL or PLL will have a faster lock acquisition time, even when there is a wide frequency range between the two clock signals.
In one embodiment, the invention includes a circuit having a first register with a first data input, a first clock input coupled to a first clock signal, and a first data output. The circuit includes a second register with a second data input coupled to the first data output, a second clock input coupled to the first clock signal, and a second data output. The circuit includes a third register having a third data input coupled, a third clock input coupled to a second clock signal, and a third data output. The circuit includes a fourth register having a fourth data input coupled to the third data output, a fourth clock input coupled to the second clock signal, and a fourth data output. The circuit includes a first logic gate, coupled to the first and third data outputs, having a first logic output coupled to a first clear input of the first register. The circuit includes a second logic gate, coupled to the second and third data outputs, having a second logic output coupled to a second clear input of the second register.
In another embodiment, the invention includes a phase logic loop circuit having an m-state phase frequency detector coupled to a reference clock signal and a feedback clock signal, where m is an integer greater than three. The circuit includes a charge pump coupled to the m-state phase frequency detector and a voltage controlled oscillator coupled to the charge pump. The voltage controlled oscillator generates a clock output. The circuit includes a divider circuit receiving the clock output and generating the feedback clock. The integer m is odd.
In a further embodiment, the invention includes a programmable logic integrated circuit having a plurality of logic array blocks, programmably configurable to perform logical functions and a programmable interconnect structure coupled to the logic array blocks. The programmable logic integrated circuit also includes a phase locked loop circuit, receiving a first reference clock signal and generating a clock output programmably coupled to the logic array blocks, where the phase locked loop circuit has a phase frequency detector circuit having m states, where m is greater than three.
The invention also includes a method of maintaining a phase relationship between a first clock signal and a second clock signal by providing a first output and a second output. A pulse is generated at the first output when a first edge of the first clock signal leads a second edge of the second clock signal. A pulse is generated at the second output when a third edge of the first clock signal leads the second edge. In one implementation, the first and second outputs are UP outputs. In another implementation, the first and second outputs are DOWN outputs.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.